In modern air combat, optoelectronic countermeasure equipment plays an important role in the war, and the infrared detection and tracking system adopts passive detection technology, so compared with active detection systems such as radar, it has strong stealth, good anti-interference ability and The advantages of high miniaturization have attracted the attention of the industry. The new generation of infrared imaging guidance system must have the characteristics of high precision, fast processing speed, strong real-time performance and short response time. This requires image processing computers to meet the large data volume, complex calculations, strong real-time performance and high transmission in image processing. Rate, stability and reliability. The article introduces the design method of infrared information data processing system based on DSP and FPGA chips from three aspects of working principle, hardware and software.
1 Overall hardware design of infrared guidance and control systemThe infrared information data processing system is divided into two major sections according to functions. The data processing system is composed of an image information processing board and a control information processing board. Its infrared guidance control information data processing system is shown in Figure 1. The image information processing board is mainly responsible for a large number of real-time image signal preprocessing, image signal processing and control tasks; the control information processing board controls the collection of interface signals, the solution of the tracking loop, the control output and the communication with the flight control computer, etc., while controlling The management module is also the management module of the system, which completes the input/output operations, synchronization control, system status management and other functions of the system.
The hardware of the image processing module is composed of reset circuit, clock circuit, image acquisition and preprocessing circuit, DSP image processing circuit, power conversion circuit and external interface circuit. The composition block diagram is shown as in Fig. 2.
2.1 Image acquisition unit
The image acquisition unit includes scanning synchronization interface circuit, detector interface circuit, front-end adjustment circuit, A/D conversion circuit, sampling control and data integration circuit, and data buffer (synchronous dual-port) circuit. The circuit composition block diagram is shown as in Fig. 2. The scan synchronization signal comes from the scan module in the system. This signal provides the system timing reference, and its signal is synchronized with the frame synchronization signal. The scan synchronization signal is connected from the backplane connector. The detector interface circuit includes: reference power supply, temperature signal, sampling control signal and 2 video analog signals, etc. The above signals are under the control of the FPGA internal acquisition circuit to ensure the synchronous acquisition of each frame of image data. The adjustment circuit adjusts the video signal output by the detector to the range of the high-speed A/D input. The differential video signal is amplified and driven by the differential driver. The common mode input voltage is the video A/D on-chip reference signal (2.5 V). Analog signal input to A/D adopts differential input mode. Video A/D is mainly used to convert analog signals and digital signals between video circuits. According to the overall requirements of the circuit, the A/D conversion circuit needs to meet the requirements of high sampling frequency, low power consumption, and high conversion accuracy. The sampling control and data buffer circuit are completed by the sampling control circuit inside the FPGA. The data buffer circuit is completed by the dual-port memory inside the FPGA, which has high-speed, synchronous and asynchronous read and write operations.
2.2 DSP image processing circuit
The DSP image processing circuit mainly includes the processor and the peripheral configuration circuit, the memory circuit and the McBSP serial circuit which communicates with the control board interface. The processor uses TI’s high-performance fixed-point TMS320C641x series C6414 GIZA-6E3 as the image information processing C6414-6E3, the clock cycle is 1.67 ns, the internal working clock can reach 600 MHz, the highest processing speed can reach 4 800 MIPS; the internal memory capacity is 8 Mbit; There are 2 extended memory interfaces, EMIFA is 64 bit, EMIFB is 16 bit, the bus frequency of EMIFA can reach 133 MHz, the maximum addressable space is 1280 MB; the core operating voltage is 1.4 V, and the operating temperature can reach -40 ~105°C. It completes the main processing algorithms of infrared imaging guidance seeker image combination, segmentation and enhancement, template matching, background processing, target extraction and target tracking.
The FPGA preprocessing unit is another core component on the image information processing board, which is implemented using XC2V2000-FG676 in the Vertex-II series of Xilinx. XC2V2000 has a scale of 2 million gates. The internal storage resources are 1 Mbit Select RAM, 336 kbit Distributed RAM, IO pin resources reach 408, and 8 DCMs. The FPGA preprocessing unit is designed by the video acquisition control and data integration unit. , Video capture buffer and main processing buffer dual-port memory, pre-processing unit, image output sub-card data transmission interface control, serial SPI interface controller, LVDS digital video output interface, host control circuit for accessing DSP/HPI interface, etc. . In addition, the FPGA configuration of the image information processing board can realize the online configuration function of the field.
The memory circuit includes two kinds of memories: Flash and FPGA internal synchronous dual-port memory. It can be connected to C6414 (EMIF external memory interface, C64 has 2 buses EMIFA and EMIFB). When in use, the EMIF bus needs to be configured through DSP/BIOS to determine the access timing. There are 2 pieces of Flash resources on the image information processing board that belong to DSP and FPGA respectively. Among them, the Flash that belongs to FPGA stores the control code on the board. The Flash that belongs to DSP is used to store the module BOOT program and also store user application programs. In order to configure the FPGA in slave and parallel mode, connect its own Flash to the C6414's EMIFB asynchronous bank CE0, using asynchronous read and write signals; to support the mechanism of C6414 booting from ROM, the DSP owned Flash is connected to C6414's EMIFB asynchronous bank CE1 using asynchronous The read and write signals. The dual-port memory is mainly used to store frame image data, and the dual-port memory is configured on the FPGA of the image information processing board. In the application, the synchronous or asynchronous dual-port memory can be configured to realize data exchange with C6414 through FPGA design. The capacity can be configured as 16 kbit & TImes; 16 bit according to the image frame size, and 16-bit or 32-bit access mode can also be configured. The dual-port memory on the image information processing board is connected to the EMIFA synchronous BANK ACE0 space of the C6414, and can be configured in synchronous or asynchronous mode.
3 Hardware design of control information processing moduleThe control information processing board is composed of processor, clock and reset circuit, memory, digital pulse counting and logic control circuit, analog to digital conversion A/D circuit and indicator circuit. As shown in Figure 3.
The signal processor of the control information processing board adopts TMS320F2812, the input working clock is provided by the 30 MHz crystal, the 16-bit bus width, the on-chip program storage space of 128 kW and the data storage space of 64 kW can be accessed, and there are three levels of external interrupts. The clock circuit uses an external crystal oscillator to provide F2812 with a 30 MHz clock input. The internal PLL circuit configures the F2812's working clock to be 120 MHz and the external bus working clock to 60 MHz. The reset circuit is output by the LDO power converter on this board, and the reset input is through the CPLD The logic control all generates the reset of the control information processing board DSP. The control information processing board mainly has the following memory configurations: F2812 on-chip memory includes: 18 kW of SARAM, 128 kB of Flash, 4kB of Boot Rom. Off-chip storage space includes: 512kB of SRAM, 1 kB of flight control computer dual-port storage Space, data registers of 3 digital pulse counting circuits and data port addresses of 2 on-board A/D converters, etc.
The programmable logic CPLD circuit completes the 3-channel digital pulse counting, reset circuit and decoding logic of the control information processing board. The decoding logic is generated by the F2812 external memory chip selection signal and the high address line through logic decoding to generate access A/ D chip and chip select signal for interface with flight control module.
CPLD realizes the principle of counting and measuring the frequency of 3 digital pulse signals; after the 3 digital pulse signals are counted by the CPLD frequency measuring circuit, they are read by F2812 regularly through software programming.
Two A/D converters realize the analog-to-digital conversion of 9 analog inputs. The A/D circuit is shown in Figure 4. The system inputs 9 differential AC analog signals. These 9 analog signals need to be adjusted to 0~+ using a differential op amp. 5 V is input to the A/D converter at the same time, and the sampling clock is controlled by CPLD.
The image control information processing system has a complex structure and numerous interfaces. Due to space limitations, only the BIT test method to verify whether it meets the requirements of the imaging guidance system and target signal processing system is briefly introduced. The A/D test uses the digital FFT method. The Flash and RAM tests use reading and writing to compare the on-chip space data to complete the judgment. The interface test uses the hardware interface to input the analog signal from the outside and then runs the software to perform the threshold judgment on the calculation result. The data transmission rate test is realized by configuring the master-slave test loop method through the EMIF bus and the synchronous dual-port RAM inside the FPCA. The BIT test result is converted to RS232 interface through RS422 interface, connected to PC for display. The test results are intuitively displayed, and local circuit failures are easy to locate.
5 ConclusionAiming at the needs of missile-borne computer infrared image information processing, a data processing system is developed with DSP (TMS320C6414) processor + FPGA (XC2V2000-FG676) as the core, and software and hardware design is carried out. The test results show that the system has strong processing capabilities, is convenient to debug, and is easy to locate when a hardware failure occurs.
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