DS28CN01 Reference Design Circuit | EEPROM Application Circuit

The DS28CN01 includes a 1024-bit EEPROM and a challenge-response authentication security scheme based on the Federal Information Council (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Hash Encryption Algorithm (SHA-1). This article mainly introduces the DS28CN01 features, application range, reference design circuit and circuit analysis to help you shorten the design time.

DS28CN01 features: 1024-bit EEPROM memory; dedicated hardware-accelerated SHA engine for SHA-1MAC; I2C and SMBus-compatible serial interface for user-programmable; support for 100kHz and 400kHz I2C communication speeds

Typical application range of DS28CN01: accessories and peripheral identification; medical sensor identification and calibration; network node identification

DS28CN01 reference design application circuit:

Figure 1 Internal structure of DS28CN01

TheDS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1).

Figure 2DS28CN01 reference design

TheDS28CN01 features a serial I2C/SMBus interface, 1Kb of SHA-1 secure EEPROM, a register page, and a unique registration number, as shown in the Block Diagram. The device communicates with a host processor through its I2C interface in standard mode or in Fast mode.

DS28CN01 Chinese data sheet: Click to download

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