Just seven steps to understand the logic analyzer test

Timing and protocol are the two key points of digital system debugging, and they are also the places where the logic analyzer can exert its value. How to use a logic analyzer to quickly complete wiring configuration and collect data? This article takes the IIC protocol as an example for everyone to demonstrate.

The logic relation of the digital system is the key in the process of communication development. It directly affects whether the entire equipment system can work normally. Although the oscilloscope can also perform partial digital signal analysis, it is limited by the number of channels (usually only 4 channels) and memory depth (smaller). Logic analyzer can reach 34 channels, the maximum record depth of up to 2G, coupled with data compression algorithm, greatly improving the efficiency of engineer test timing analysis.

Take IIC as an example below to share the logic analyzer test procedure.

I. Preparation

The test is mainly measured object, logic analyzer, computer, IIC protocol signal.

The logic analyzer uses the standard power adapter and presses the power button. Connect the instrument to the PC with a USB cable and open the software to see if there is an "online" at the top of the software interface. Connect the IIC protocol (amplitude 3.2V, frequency 50KHz), use A1 from the measurement line PODA to SCL, A0 to SDA, and make sure that the signal ground is connected.

II. IIC bus settings

1, click on the bus name can modify the bus name, it is recommended not to have duplicates;

2, the bus name is best related to the meaning of the channel;

3, do not add the same bus, the software will filter them out;

4, do not increase the bus without channels;

5, the useless bus is deleted in time, it looks more concise.

Set effect as shown in Figure 1:

Figure 1 IIC channel open

Third, the IIC sampling parameter settings

1. Sampling mode: The difference between synchronous and asynchronous, synchronous sampling advantages;

2. Sampling frequency: The sampling frequency is generally set to 4 to 5 times of the measured signal, and it needs 20 times or more when protocol decoding is required. Decoding error will occur if the sampling rate is not enough. Synchronous sampling should be used for high frequency of measured signal;

3, storage depth: channel reuse, segmented storage, compressed storage, recording mode (real-time storage);

4, threshold voltage: generally set to 1/2 (MAX + MIN);

5, filter settings: bus filtering, filtering a glitch signal sampling cycle. Channel filtering, filtering 1~2 sampling cycles. Bus filtering and channel filtering are hardware filters.

The setting effect is shown in Figure 2:

Figure 2 parameter settings

IV. IIC Trigger and Decode Settings

1, the name is set to custom;

2, the input bus corresponds to a good channel;

3, the bus set a good address bit.

The setting effect is shown in Figure 3 and Figure 4:

Figure 3 trigger settings

Figure 4 Property Configuration

V. IIC decoding analysis results

Start collecting and storing a piece of data for parsing.

1. The data segment area reflects the specific data analysis waveforms in the results;

2. The waveform observation mode can be set through the waveform display settings;

3, through the waveform zoom can observe the specific frame propagation content produced at different times;

4. The schedule display area will logically parse and transform the contents of the entire data segment.

The test results are shown in Figure 5:

Figure 5 Decoding Analysis

Six, IIC decoding data search

1, find the bus: IIC;

2, start time: Ds, A, B;

3, the end time: Dp, A, B;

4, compare the frame type: can choose;

5, data: You can enter the corresponding frame type data decimal, hexadecimal, octal.

Set the effect as shown in Figure 6:

Figure 6 Frame Lookup Property Settings

Seven, accurate positioning of decoding data

After completing the settings, you can display by looking for specific search types. The results are shown in Figure 7.

Figure 7 Finding Results

There are a total of 68 search results for this search, and each search result can be observed through the following operations. The results are shown in Figure 8:

Figure 8 Finding Results Data Analysis

ZLG Zhiyuan Electronic Logic Analyzer has large capacity storage, intelligent filter storage, high fidelity uninterrupted real-time recording, an efficient protocol analysis platform, multiple trigger search, and flexible parameter measurement. It can locate specific waveform data when the system runs in error. For the development and testing of digital circuits, a logic analyzer can be used to perform accurate state or timing analysis on the circuit to detect errors in the analysis circuit design, thus quickly locating and resolving problems.