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Digital Video technology will undoubtedly reshape the entire electronics industry. Of course, digital video technology is also making profound changes to our video experience, transmission and interaction, starting to enter cars, computers, mobile phones and networks. In the past, engineers had very limited choices when implementing digital video. Hard-wired and ASIC-based solutions always limited the device's purpose, functionality, and their adaptability; while dedicated devices were slightly more flexible than ASICs, In the face of ever-changing multimedia standards and applications, their utility is still limited; and there is a lack of digital video development platforms with sufficient performance, low cost, and high enough flexibility.To address these challenges, Texas Instruments offers a great solution for simplifying digital video innovation based on DaVinci technology and its products, such as the TMS320DM6446. Includes two digital signal processor (DSP) based system-on-a-chip (SoC) and multimedia codecs, application programming interfaces (APIs), frameworks and development tools. These integrated components are the industry's first, complete, open platform products that enable digital video innovation without the need for extensive digital video expertise. For products using DaVinci technology, adding video functionality to an application becomes as simple as API programming, saving OEMs months of development time and dramatically reducing overall system cost.
DaVinci technology
DaVinci technology is optimized by components such as DaVinci processor, DaVinci software, DaVinci development tools and DaVinci technology support systems. Among them, the DaVinci processor is based on the industry's highest performance DSP platform - TI TMS320C6000, which utilizes TI's latest C64x+ DSP core. DaVinci processors include scalable, programmable DSP-based SoCs (customizable from DSP and ARM cores), as well as optimized accelerators and peripherals to meet the price and performance of a wide range of digital video end equipment And the needs of many aspects such as functions.
DaVinci software running on the DaVinci processor leverages chip resources. It is built into a configurable framework and is delivered through published APIs within popular operating systems for fast software implementation.
DaVinci technology provides a range of tools and kits for a wide range of applications and designs, including low-cost starter tools, complete development kits, and reference designs to accelerate OEM design and development. The ARM/DSP Integrated Development Environment (IDE), operating system tools, and DSP tools enable developers to program in a familiar environment while gaining the benefits of DaVinci technology.
To accelerate the time-to-market for OEMs, DaVinci technology's support systems include end-to-end video environments, system integrators, and hardware and software solution providers with DaVinci technical knowledge and video system expertise. The TMS320DM6446 chip is an outstanding representative of DaVinci technology.
Structural features of TMS320DM6446
The structure of TMS320DM6446 is shown in Figure 1.
Structural features
(1) High performance. Low-power, high-performance 32-bit kernel and TMS320C64x ARM926EJ-S core, respectively, the operating frequency of up to 594MHz and 297MHz; support multimedia processing, is used in the DSP TMS320C64x core, to enhance the ability to decode video and Audio.
(2) Low power consumption. Multiple power management mode, dual-core supply voltage is 1.6V; ARM926EJ-S core has 16KB and 8KB instruction data Cache, TMS320C64x DSP core has a 32KB program RAM / Cache, 80KB data RAM / Cache undefined and 64KB RAM / Cache; 3.3 Support V or 1.8V I/O interface and memory interface.
(3) Dedicated video image processor and video processing subsystem. A dedicated video image processor is used to process the video data; the video processing subsystem includes a video front end input interface and a video end output interface, and the video front end input interface is used to receive images such as an external sensor or video decoder, and the video end The output interface outputs images to SDTV, LCD, HDTV, etc.
(4) Storage capacity. There are 256MB of 32-bit DDR2 SDRAM storage space and 128MB of 16-bit FLASH storage space.
(5) Numerous peripherals. 64-channel enhanced DMA controller; serial port (3 UARTs, SPI, audio serial port); 3 64-bit general-purpose timers; 10/100M Ethernet; USB2.0 port; 3 PWM ports; up to 71 A general-purpose I/O port; support for MMC/SD/CF cards, etc.
(6) Clock control. Clock source: 27MHz system oscillator; 24MHz USB oscillator.
ARM926EJ-S kernel
The ARM926EJ-S core is a 32-bit RISC processor with a pipelined pipeline and is equipped with a Thumb extension. It can handle 32-bit or 16-bit instructions and 8-bit, 16-bit, 32-bit data. It enhances the architecture by using the coprocessor CP15 and protection modules and provides data and program memory management units (MMUs).
The MMU has two 64-bit translation bypass buffers (TLBs) for instruction and data streams, each of which maps segments of memory, large pages, and small pages. In order to guarantee the access instructions and data of the kernel cycle, a separate 16K byte instruction cache and 8K byte data cache are provided, and the instruction and data cache are connected through the VIVT four-way. In addition, a write buffer is provided to improve core performance with a buffered data capacity of up to 17 words.
TMS320C64x DSP core
TMS320C64x DSP core architecture built on VelociTI.2 on VelociTI.2 is further enhanced architecture, with its advanced C64x core of very long instruction word (VLIW) architecture, very high-performance applications to obtain current needs.
The structure is characterized by: 1) C64x has 2 data channels, 8 functional units and 2 general purpose register files (A and B). The 8 functional units and 2 register files are divided into the same two groups, each group occupies one data channel. There are two data cross paths between the two data channels. 2) The C64xDSP uses a very long instruction word (VLIW), which provides up to eight 32-bit instructions per clock cycle, and an instruction packet with a total word length of 256 bits is simultaneously allocated to eight parallel processing units. At a clock frequency of 594 MHz, when the eight processing units on the chip are running simultaneously, the maximum processing power can reach 4800 MIPS. 3) C64x DSP has dual 16bit expansion function, the chip can complete double 16-bit multiplication, addition, subtraction, comparison, shifting and other operations in one cycle. The C64x accelerates communication and imaging applications by compressing DSP operations in fewer cycles. In an extension to enhance parallelism, four sets of 8 bits/two sets of 16-bit instructions allow approximately 9 billion 8-bit multiply-accumulate period (MAC) operations per second.
System control function
The system control module of the TMS320DM6446 microprocessor provides a watchdog (WT), an interrupt controller, a power management controller, a reset controller, and two on-chip oscillators.
Video Processing Subsystem (VPSS)
The video processing subsystem in the TMS320DM6446 has two interfaces, a video front-end input (VPFF) interface for video input and a video end output (VPBE) interface for image output.
The Video Front End Input (VPFE) interface consists of a CCD controller (CCDC), a preprocessor, a columnar module, an auto exposure/white balance/focus module (H3A), and registers. The CCD controller can be connected to a video decoder, CMOS sensor or charge coupled device; the preprocessor is a real-time graphics processor that converts raw graphics from CMOS or CCD from RGB (three primary colors) to YUV 4:2:0 encoding The columnar module and the H3A module provide raw graphical information.
The Video End Output (VPBE) interface consists of an online video display processor (OSD) and a video encoder. The online video display processor can display two sets of independent video windows or two independent OSD windows, and can also display in the form of one video window, one OSD window and one property window. The video decoder performs D/A conversion at 54MHz and can provide video or audio output in NTSC/PAL, S and other formats.
The power management TMS320DM6446 has three power management modes: standby power mode, low power operation mode, and normal operation mode. The power consumption in standby power mode is the lowest, neither the DSP core nor the video processor subsystem is running. Except for general-purpose I/O, UART, and PWM operations, other peripherals are not running, and only the 27MHz clock is active. In low-power mode, only some of the basic functions of ARM are run, and the DSP core and video processor subsystems are not running. Except for general-purpose I/O, UART, PWM, SPI, and timer operations, other peripherals are not running. It runs, and it only works with a 27MHz clock. In normal operation mode, the two clocks operate normally except that all modules and peripherals can be operated.
External memory interface
There are several forms of external memory interfaces in the TMS320DM6446: asynchronous EMIFA (NOR Flash, SDRAM), NARD Flash, and CF card. The asynchronous EMIFA includes an 8-bit or 16-bit data line, a 24-bit address bus, and four dedicated chip select lines. The supported memory interfaces include NAND, ATA/CF, and host-side interfaces. The NAND interface includes storage types such as NAND cards, SM cards, and xD cards. DDR2 memory controller for connection with a 16-bit or 32-bit DDR2 SDRAM. DDR2 SDRAM plays an important role in DaVinci technology. It can be used to buffer video input graphics data, as an OSD buffer, and store ARM and DSP code.
Peripheral control module
The TMS320DM6446 has three 64-bit general purpose timers and three PWM modules. Timers 0 and 1 have a 32-bit general-purpose timer mode, Timer 2 has a WD mode, and generates ARM and DSP interrupts to generate an EDMA synchronization event. The PWM module can be used for both periodic counting and repeated counting.
The TMS320DM6446 microprocessor has 64 independent channel advanced DMA controllers. The DMA controller is used to respond to requests from internal and external devices. In the MPU TI926 (ARM926EJ-S) operating condition, to complete the data transfer between the external register / registers internal and external devices. The DMA settings depend on the MPU TI926 (ARM926EJ-S) core.
The GPIO peripheral controller can configure the general purpose pin as an input or output. When configured as an output pin, the internal register can be written to control the state of the output pin. When configured as an input pin, the status of the input can be known by reading the status of the internal registers. In addition, GPIO peripherals can generate CPU interrupts and DMA events. The GPIO pins are in 16 columns. The functions supported are as follows: 54 1.8V GPIO pins and 17 3.3V GPIO pins. There are 8 GPIO[0:7] interrupts in each column starting from the O column. A rising or falling edge triggers an interrupt, etc.
TMS320DM6446 supports a variety of serial interfaces: (1) 3 UART interfaces, of which UART2 has the function of: 16 bytes of storage space for the receiver and transmitter FIFO, DMA can receive data and send data. Programmable automatic send request and automatic clear request during automatic control, and internal diagnostics. (2) SPI peripherals, which provide a programmable length register that is connected to other SPI devices via a 3- or 4-wire interface. (3) Interfaces that can be connected to their devices that comply with the bus 2.1 protocol. In the mode, 8-bit data can be transmitted/received through two serial buses. (4) Audio serial interface (ASP), the function of the ASP module is: full-duplex communication, directly connected with the media digital signal codec, A/D, D/A, etc.
In addition, there is a USB2.0 interface. USB2.0 has the following features: high-speed 480Mb/s and full-speed 12Mb/s transmission as peripherals, high-speed, full-speed and low-speed transmission as a host, and standard UTMI+ PHY Interface connection, there is 4K programmable RAM in the FIFO.
The Ethernet Controller (EMAC) module provides an interface between the network and the chip, supports 10M/100M Ethernet access, supports hardware flow control and QOS.
The Data Input/Output Management (MDIO) module is used to manage the PHY devices connected to the chip. The host software uses the MDIO module to configure the parameters of each PHY corresponding to the EMAC, and retrieves the corresponding result, so as to configure the required parameters in the EMAC module.
Da Vinci technology and its chip application and development prospects
Because DaVinci technology successfully implements digital video with the latest advances in four elements: processors, development tools, software, and system expertise, DaVinci technology lays the foundation for the current revolution in digital video.
Significantly reduce system costs
DaVinci technology utilizes digital signal processing and integrated circuit expertise to provide highly integrated system-on-chip (SoC) with integrated programmable digital signal processor (DSP) core, ARM processor, video acceleration coprocessor, memory, I /O bandwidth, balanced internal interconnects, and a combination of dedicated peripherals reduce hardware bill of materials costs by 50%.
Hardware and software for digital video subsystems with integrated code
To truly enable developers to overcome initial barriers and speed time-to-market, the complete DaVinci software architecture covers low-level OS drivers and even application APIs, eliminating the need for developers to write and optimize codecs or DSP programming enables digital video capabilities, allowing developers to focus on developing products that maximize added value. For example, in the past, when developing electronic devices, even the most basic functions, engineers needed to make gate layouts; now developers no longer need to understand the implementation of specific CODEC engines in their video applications (eg MPEG-2, H. 263, WMA9) details, developers can use the ideal CODEC API without modifying the upper application code, significantly simplifying the specific low-level details of video CODEC processing, so that developers can be based on the development of functionality.
By providing software that can be put into production at any time, such as hardware drivers, manually optimized CODECs, and an overall combination of application code for managing audio/video synchronization and data streaming in the network, DaVinci technology eliminates the need for developers to understand how to program DSPs. Achieve first-class video capabilities.
Open platform development
The complexity of digital video systems is primarily attributable to the many components that developers must create and manage. DaVinci technology reduces system complexity by providing an open platform on which TI and its third-party partners have developed and integrated the various components needed to form a digital video system. The open development platform provided by DaVinci technology also extends to applications. DaVinci software will initially support Linux and will continue to support other operating systems in the future. Linux-backed content includes peripheral drivers, real-time application management, application-level APIs, and code that is ready to go.
Conclusion
DaVinci technology is a major milestone in consumer electronics, driving the growth of new digital video applications and making existing applications easier to use.
DaVinci technology will fully meet the demand for real-time video from many emerging digital video innovations. These applications include video security surveillance systems, IP set-top boxes, video conferencing, in-vehicle infotainment systems, portable media, and digital cameras.
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