introduction
The current mainstream product in the field of security monitoring is DVR (Digital DVR), whose main feature is suitable for local monitoring applications where monitoring points are concentrated. However, with the growing demand for remote distributed monitoring, embedded network video servers are increasingly valued by security vendors and customers for their high reliability and convenient networking. Video server solutions have many options, but the mainstream of market products generally choose two options: (1) CPU + ASIC. The solution chooses an ARM-based CPU and a dedicated media processing chip. The advantage is that the development time is relatively short, but due to the ASIC, the flexibility is poor, and once the product is finalized, it is difficult to change. (2) A dedicated DSP for media processing. The development time is not long. The advantage is that since the algorithm is software code, the performance of the product can be continuously upgraded, and the cost of repeated development is low. Based on the above points, the system adopts the second scheme design.
one. The hardware design of the system.
The main function of the video server is to complete the function of image, sound collection, compression and transmission. The core technologies used by video servers generally include video compression algorithms, audio compression algorithms, and network transmission protocols. At present, the mainstream technologies on the market are mainly MPEG4 or H26x video compression algorithms, AAC audio compression algorithms, G.72x voice compression algorithms (or AAC audio compression algorithms), TCP/IP protocols, and the like. DM642 is a DSP developed by TI for multimedia processing applications. It is based on C64x and adds many peripheral devices and interfaces. The DSP is a 548-pin BGA package that is highly integrated. The main peripherals include: Three configurable video interfaces that seamlessly interface with video input, output or transport stream inputs. VCXO Interpolation Control Port (VIC) 10/100Mbps Ethernet Port (EMAC). Data Management Input and Output Module (MDI0). Multi-channel audio serial port (McASP). I2C bus module. Two multi-channel cached serial ports (McBSPs). Three 32-bit general purpose timers. User configurable 16-bit or 32-bit master port interface (HPI16/HPI32). 6Mhz32-bit PCI interface. General purpose I/O port ((GPIO). 64-bit external memory unit interface that supports connection to synchronous or asynchronous memory locations.
The system hardware block diagram is as follows:
This system is designed with 3 channels of video port, 2 board decoder and 1 board encoder, 32Mbytes synchronous DRAM through FPGA OSD 4Mbytes Flash memory, 10/100 Ethernet port is imported through the board software configuration of the FPGA internal register Load option configuration. The DSP chip connects the on-board peripherals through a 64-bit EMIF interface or an 8/16-bit 3-way video interface. Each device of SDRAM, Flash, FPGA, and UART occupies one of these interfaces. The EMIF interface is also connected to the expansion backplane interface, and the extended backplane interface is used to connect the backplane. The on-board video decoder and encoder are connected to the video port and expansion connector. The two encoders and one decoder on the motherboard meet the standard specifications. McASP can be reconfigured as an extension interface via software. Programmable Logic Gate Arrays, also known as FPGAs, are used to execute logic programs that are grouped together on a board. The FPGA has a register based on the software user port. The user can read and write this register to configure the board.
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