Because the market's requirements for MCU functions are constantly changing and upgrading, and the field of MCU applications is also constantly expanding, it is often necessary to modify the original design. Compared with the previous OTP/MASK MCU, the biggest advantage of Flash MCU is that it can perform up to tens of thousands of erasing and writing operations, which conforms to the demand for continuous modification of MCU functions; on the other hand, the market price of Flash MCUs is also declining. In fact, the delay and charging time of Flash during the operation of Flash MCU are very different. The program is stored in the SRAM on the external simulation board of the MCU. It is time-consuming and inefficient to simulate these characteristics of Flash by additional hardware logic; At the same time, it is also very important to distinguish Flash from other types of memory embedded in MCU, such as SRAM and ROM. If this feature can be reflected in the debugging stage of the program, it is also useful to realize the seamless transfer of the program from the emulator to the commercial MCU chip.
The structure of Flash MCU is shown in Figure 1. It is mainly composed of CPU core, Flash IP and its control module, SRAM IP and base control module, WatchDog, PMU (Power Manage Unit), I/O port and ISP online Programming interface and other components. Flash MCUs with different functions also include some unique application module units, such as a decoding module included in the Flash MCU for paging. The Flash MCU used to form an online emulator may also include an emulation interface unit. When discussing the online emulation of Flash MCU, this article refers to all Flash MCUs that contain emulation interfaces.
Flash memory has almost all the advantages needed by users who are pursuing personalization today: no data loss after power failure, fast data access time, electrically erasable, large capacity, online (system) programmable, low price, and enough The high reliability of erasing and writing times, etc., has become the first choice for a new generation of embedded applications. Compared with Flash MCUs, although MASK (mask) MCUs still have a certain price advantage in the production of the big finger, but its shortcomings of inconvenience to upgrade, as the cost of Flash decreases and the demand for MCU functions gradually increases in the future, it will perform More significant.
2 MCU online emulator based on external SRAMSRAM can save the data stored in it without refreshing the circuit. And DRAM (Dynamic Random Access Memory) needs to be refreshed and charged every once in a while, otherwise the internal data will disappear, so SRAM has higher performance, but SRAM also has its shortcomings, that is, its integration is low, the same The capacity of DRAM memory can be designed into a smaller volume, but SRAM requires a large volume and consumes a lot of power. Therefore, the SRAM memory on the motherboard takes up a part of the area.
One is the cache between the CPU and the main memory. It has two specifications: one is the cache (Cache Memory) fixed on the motherboard; the other is the COAST (Cache ON A) inserted in the card slot. Stick) the high-speed cache for expansion. In addition, in the circuit of the CMOS chip 1468l8, it also has a smaller capacity 128-byte SRAM inside to store the configuration data we set. Also in order to speed up the transmission of data within the CPU, since the 80486CPU, a cache is also designed inside the CPU, so there are so-called L1 Cache (first level cache) and L2Cache (second level cache) terms in PenTIum CPU Generally, L1 Cache is built in the CPU, L2 Cache is designed outside the CPU, but PenTIum Pro designs both L1 and L2 Cache inside the CPU, so PenTIum Pro has a larger volume. PenTIum II moved the L2 Cache to a black box outside of the CPU core.
A common practice of MCU emulators is to store the user's program to be debugged (hereinafter referred to as the user program) in the SRAM (hereinafter referred to as external SRAM) of the MCU external simulation board, and simulate the monitoring hardware in the external structure of the bond-out MCU ( Hereinafter referred to as external simulation logic), when the user program is debugged in the emulator, it is programmed into the commercial MCU chip and applied to the user system. In commercial MCUs, these simulated interface signals do not appear on the pins of the chip package.
Before Flash MCU was widely used, emulator design companies usually stored user programs and monitoring programs in external SRAM. This approach can basically reflect the real operating conditions of SRAM MCUs, and has little effect on the scheduling effects of user programs. . But for Flash MCU, there are certain problems. Bijing SRAM and Flash are far apart in process and read/write timing. The CPU runs the programs stored in SRAM and Flash, and the situation is completely different. It is possible that the external SRAM of the emulator for program storage works well, but it does not work normally when programmed into a commercial MCU. With the increasing proportion of Flash MCUs in the MCU market, this problem has become more and more prominent and it is necessary to pay attention to it.
The design method of the Flash MCU emulator introduced in this article hardly increases the complexity of the MCU's simulation interface signals and chip design, and can approach the program's operation in a commercial MCU, and realize a good transfer of the user program from the emulator to the commercial MCU. .
3 A design method of an online simulator based on the internal Flash of the MCUFigure 2 is a schematic diagram of the system structure of the Flash MCU emulator. The dotted interface signal is the emulation interface of the MCU, which usually includes the emulation enable signal, the address, data, read/write, and fetch signals of the CPU in the bond-out MCU. And a few control signals for simulation. The simulation interface is a bridge between the Flash MCU and the external simulation logic, enabling the external simulation logic to monitor the internal state of the MCU.
3.1 The working principle of the simulator
The hardware resources such as the P port inside the emulator are basically completely compatible with the 51 series single-chip microcomputer. The emulation main control program is stored in a special designated space of the emulator chip. There is a special address segment used to store the emulation main control program. The emulation main control program controls the correct operation of the emulator just like the operating system of a computer. The emulator and the host computer software (ie KEIL) on the computer are connected through the serial port. The RXD and TXD of the emulator chip are responsible for receiving the control data sent by the host computer, and the TXD is responsible for sending feedback information to the host computer. The control command is issued by KEIL, and the simulation main control program inside the simulator is responsible for executing the received data and performing correct processing. Then drive the corresponding hardware work, which also includes storing the received BIN or other formatted program in the emulator chip to store the executable program storage unit (this process is similar to burning the program into the 51 chip Yes, it's just that the erasing of the emulator is done in the form of overwriting), so that the function similar to the programmer's repeated programming to test is realized! The difference is that by simulating the main control program, these target programs can be run in a specific way, such as single step, designated breakpoint, designated address, etc., and the state of each memory unit inside the single-chip microcomputer can be observed from time to time through KEIL. After the emulator and the host computer are online, it is like two precision gears are engaged with each other. If the connection is forcibly interrupted (for example, the emulator is manually reset or the connection line is dialed, etc.), the computer will prompt that the connection appears. The problem, this also reflects the characteristics of hardware simulation, that is, "what you see is what you get". These are things that the programmer cannot do. These create a stronger guarantee for debugging, modifying, and generating the final program, so as to achieve higher efficiency.
When the emulator is working, the fetch space of the CPU needs to be repeatedly switched between internal and external memories. The schematic diagram of CPU address space division is shown in Figure 3. In general, the work of the simulator is controlled by the state machine shown in Figure 4. The state machine has four states:
• User program running state (referred to as user state)
After the emulator is reset, it is in the state of running the user program. In this state, the CPU runs the user program stored in the internal Flash; the external simulation logic monitors the simulation interface in real time, waits for the occurrence of the program interrupt event, and enters the next state-the jump state.
The user program is programmed into the internal Flash through the ISP (Online Programming Interface) of the MCU and is completed by the dedicated programmer of the Flash MCU. When designing a bond-out MCU, you should consider the pin consistency of the programming with a non-bond-out MCU.
External SRAM is used to store monitoring programs and time-monitoring data.
• Jump state
Once the program interruption event occurs, you need to switch the fetch space of the CPU and jump to the monitor program window.
Because the interruption in the program is unpredictable, it is impossible to pre-install the jump instruction for space switching in the user program. Therefore, a special state is needed to insert the jump instruction code and the destination address of the jump, that is, the entry address of the monitoring program, to force the CPU to run the monitoring program. The monitoring program window is the address space reserved for the simulation function when the CPU address space is divided. The size of the space depends on the size of the required monitoring program. The size of the monitoring program depends on the strength of the simulation function in a certain program.
The CPU reads the jump instruction code and jump address from the simulation interface. The MCU external simulation logic also enables the program space switching signal, shields all external interrupts of the MCU, and stops the clock of the CPU peripheral module in the MCU, which is equivalent to shielding all the internal interrupts of the MCU. When the switching of the program space is completed, the emulator enters the monitoring state and runs the monitoring program stored in the external SRAM.
•Monitoring state
In the monitoring state, the CPU runs the monitoring program stored in the external SRAM; continues to prohibit all external interrupts of the MCU, and stops the clock of the CPU peripheral hardware module in the MCU.
The task of the monitoring program is to obtain the current status of the MCU, accept the debugging commands of the software, and control the next operation of the MCU. The monitoring program can be written very simply, only to obtain the values ​​of the CPU special registers and peripheral hardware registers to realize the monitoring function. For example, HC6808 of MOTOROLA can get the value of these registers by adding the following program segment at the beginning of the monitoring program. For MCUs whose CPU instruction set does not support reading all special registers, it can be obtained by adding test logic inside the MCU. The PC value is the fetch address of the CPU where the program is interrupted.
PSHA; push the value of ACC onto the stack
TPA; transfer the value of CCR to ACC
STA $2FEB; store the value of CCR in the memory, the address is $2FEB
PULA; pop ACC from the stack
STA $2FEA; store the value of ACC in the memory, the address is $2FEA
STHX $5F; store the value of IDX (H:X) into the memory, the address is $005F
TSX; transfer the value of SP to IDX (H:X)
STHX $5D; store the value of SP in the memory, the address is $005D
When the debugging is no longer continued, the command to start running is given, the monitoring program ends waiting for the running command, and the value of the CPU special register is restored. Continue to run the monitoring program until the last instruction, the jump instruction, returns to the state.
• Return state
The CPU executes the last instruction of the monitoring program-a jump instruction. The external simulation logic inserts the interrupt point address of this interrupt event (the user program instruction address before entering the monitoring program) immediately after the instruction code, and the instruction fetch space of the CPU needs to jump back to the user program space. Cancel the shielding of the external interrupt, restore the working clock of the CPU peripheral module, the monitoring program completes its mission, returns to the user mode, and continues to run the user program in the internal Flash.
3.2 Internal simulation logic
In order to construct a suitable MCU emulation interface, it is necessary to add an emulation interface module inside the MCU when designing the MCU, which is called an internal emulation interface module. Responsible for processing the CPU port signals required by the simulation interface (for example, to reduce the bond-out signal line, multiplexing the address and data bus), and generate the control signals required by the external simulation logic such as the address latch signal, Receive control signals from external simulation logic, such as switching enable signals between program diplomas.
3.3 External simulation logic
The external simulation logic is shown in the left part of Figure 2, which is responsible for receiving simulation commands sent by the computer through the parallel port, monitoring the simulation interface of the MCU, and controlling the working status of the simulator. The external simulation logic is composed of an external simulation interface module, a breakpoint judgment module, a track record module, a parallel port interface module, and an external SRAM read-write control module. The function of each module is briefly introduced as follows:
• External simulation interface module
This module is the core module where the simulation state machine is located in the external simulation logic. Functions include: receiving the address, data, read/write, instruction fetching, address latch and other signals from the MCU; according to the simulation command from the software given by the parallel port interface module, and receiving the breakpoint flag signal from the breakpoint judgment module ; Generate the program space switching enable signal sent to the MCU; when running the monitoring program, give the signal required to read and write the external SRAM, and receive the read data, and send it to the MCU.
•Breakpoint judgment module
According to the CPU address sent by the external simulation interface module, read the corresponding value in the breakpoint mark memory. If the read flag is a valid value, it means that the current address is a break address. Receive the set and clear breakpoint commands from the parallel port interface module, and set the corresponding position in the breakpoint memory to 1 or 0. Allow any number of hardware breakpoints to be set.
•Track record module
The CPU instruction address sent by the external simulation interface module is stored in the memory of the track record. The track record memory adopts the FIFO mode, and the track length that can be recorded is limited, and the memory is refreshed when it is full. The software reads the memory and can get the running track of the CPU.
•Parallel interface module
Parallel interface (parallel interface), referred to as parallel interface, also known as LPT interface, is an extended interface using parallel communication protocol. The data transfer rate of the parallel port is 8 times faster than that of the serial port, and the data transfer rate of the standard parallel port is 1Mbps. The parallel port uses a 25-pin D-shaped connector. The so-called "parallel" means that 8 bits of data are simultaneously transmitted through parallel lines, so that the data transmission speed is greatly improved, but the length of the parallel transmission line is limited, because the length increases, the interference will increase, and the data is prone to errors. At present, the parallel interface is mainly used as a printer port and so on.
Provides a communication interface between the emulator and the parallel port of the computer, which can be designed for different parallel port modes to meet the communication timing requirements of different modes.
• External SRAM read and write control module
During the simulation process, different parts of the emulator need to read and write external SRAM in time-sharing, including: parallel port interface module downloading program to external SRAM; MCU reads program instructions from external SRAM in monitoring mode, and stores temporary data.
For Flash MCU, the user's program to be debugged is stored in the Flash inside the MCU, the monitoring program is stored in the SRAM outside the MCU, and the simulation logic is constructed outside the MCU. The bond-out pin is monitored to realize the online simulation method. There is no need to do too much work in the chip design, and it can reflect the real running effect of the program. Compared with using a hardware platform such as FPGA simulation, the price is much lower, and it is a way of weighing compromises. The author extracted a simple Flash MCU model, used this method to complete the logic design of the simulator, synthesized it with Synopsys DC, used Quartus wiring in Altera APEX 20K200 FPGA, and performed post-simulation with ModelSim5.4 to complete the simulation verification. It turns out that this approach is feasible.
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