In general, in a fully synchronous design, if the signals are from the same clock domain, the inputs to each module do not need to be registered. As long as the setup time is met and the time constraint is maintained, it can be guaranteed that the input signal is stable when the rising edge of the clock arrives, and the correct value can be sampled. But if the module needs to use the edge of the input signal (such as the frame sync signal), don't do this directly.
Always @ (posedge inputs)
Begin
...
End
If this input signal comes from an asynchronous clock domain (such as an input external to the FPGA chip), two shots must be registered. The first beat synchronizes the input signal, and the synchronized output may cause a setup/hold time conflict that produces a metastable state. Need to register another shot to reduce (note the reduction) the effect of metastability.
If this input signal comes from the same clock domain and a transition edge is needed, a shot is required. Otherwise, the timing report will mostly report clock skew > data delay, causing a conflict in setup/hold time.
All in all, the five principles: 1. The global clock has the most reliable transition edge.
2. Inputs from the asynchronous clock domain need to be registered once to be synchronized, and then re-registered to reduce the effects of metastability.
3. It is not necessary to use the input of the same clock domain from the edge of the transition. It is not necessary to register the signal.
4. Need to use the input of the same clock domain from the edge of the transition, register once.
5. The input from different clock domains is required to use the transition edge. Three flip-flops are needed. The first two are used for synchronization. The output of the third trigger and the second output are judged by logic gates. Change edge.
Always @ (posedge Clk) //Do not register the input signal
Begin
If (inputs)
Begin
...
End
...
End
Always @ (posedge Clk) //Register a call to the input signal
Begin
Inputs_reg <= inputs;
If (inputs_reg == 1'b0 && inputs == 1'b1)
Begin
...
End
...
End
Always @ (posedge Clk) //Register three shots on the input signal
Begin
Inputs_reg1 <= inputs;
Inputs_reg2 <= inputs_reg1;
Inputs_reg3 <= inputs_reg2;
If (inputs_reg2 == 1'b1 && inputs_reg3 == 1'b0)
Begin
...
End
...
End
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