Veloce hardware accelerated simulation platform software joins ISO 26262 verification program

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Mentor, a Siemens business announced that the independent compliance company SGS-TüV Saar has ISO 26262 compliance certification for the tool validation report for the key software elements of Mentor's new Veloce® StratoTM hardware accelerated simulation platform. Certification strengthens Mentor's leadership in ensuring functional safety and hardware accelerated simulation technology, enabling chip designers to meet and exceed the increasingly stringent safety and quality requirements of the global automotive industry.

This is the 22nd time that Mentor has passed the ISO 26262 product certification. As seen in the new features of these Mentor Safe programs, the company is committed to enabling all of its flagship products in the industry's leading portfolio of electronic hardware and software design solutions to pass functional safety verification of key documents.

“People's demand for autonomous driving and sophisticated ADAS systems is constantly changing the global automotive industry. The world's leading automotive manufacturers and their suppliers are increasingly demanding pre-certified design automation technologies and documentation to reduce time to market and ensure the most "Good cost-effectiveness," said Eric Selosse, vice president and general manager of Mentor Hardware Acceleration Simulation. “To address this need, Mentor has introduced platforms and solutions that simplify the development, design and creation of automotive-grade ICs with the Mentor Safe ISO 26262 validator.”

Mentor's Software Tools Validation Report provides documentation that includes hypothetical use cases and evidence to demonstrate that the Validation Software Tool is applicable to any Tool Confidence Level (TCL) activity or ISO 26262 required tasks. SGS-TüV Saar has ISO 26262 compliance certification for the following software elements of the new Veloce Strato hardware accelerated simulation platform:

Veloce Strato OS, extensively using advanced techniques and methods for high-quality verification of system-level, capable RTL and GL hardware descriptions. It allows users to manage the entire verification process, measure progress metrics, and use advanced incentives to quickly reach coverage goals. Veloce Strato OS enables users to compile and emulate composable hardware models written in VHDL, Verilog, and SV languages, as well as a variety of non-integratable test platform environments written in VHDL, Verilog, SV, C, C++, and SystemC.

The Veloce Fault App, which allows users to inject errors into the design to simulate random environmental events that can cause circuit failure. The application enables customers to test and evaluate system security vulnerabilities in the design to provide protection before problems occur.

The Veloce Coverage App, which enables hardware accelerated emulation users to collect statistics by assertion coverage, feature coverage, and code coverage during hardware accelerated emulation.

The Veloce DFT App, which accelerates the verification of testable designs, fully validates test vectors and DFT logic before chip streaming, improving confidence, reducing risk and reducing chip turn-on time.