Engineering design of portable power supply - Power Circuit - Circuit Diagram

Providing mobility to products can bring additional benefits and open up emerging markets beyond existing applications. The portable ultrasound device market is a good example. So far, ultrasound image examination still needs to go to the clinic to complete. In most developed countries, this is usually not a problem. However, in some remote villages and towns, if the equipment can be transported directly to the patient, it will greatly improve the local medical environment. When designing mobile devices, the trade-offs between weight, size, and operating time are challenging tasks. When the conventional power conversion efficiency exceeds 90%, many engineers will choose to redesign the board to seek greater efficiency improvement space from different functional perspectives, thus reducing overall power consumption.
Low-fruit first picking In general, the opportunity to find power gains should start with the most obvious or easiest place. When the power conversion efficiency is between 60% and 75%, the maximum power gain comes first from the conversion from the linear regulator to the switching regulator, which will greatly improve the overall efficiency of the system. Today, integrated high-efficiency switching regulators are available, and engineers must find new breakthroughs beyond power conversion.
Size, weight, heat dissipation and cost are all drivers of the mobile market, and these factors often have an impact on the decision-making process. At present, the battery is a weak link in the system, and it is unable to keep up with the development speed of semiconductor process technology. As modern power supplies continue to improve, the next opportunity to reduce power loss will come from the system architecture itself. In recent years, Intel and other CPU manufacturers have come to realize that speeding up CPU speed may not be the best way to improve performance. The main problem they face is the heat of the processor and the dynamic requirements of the peripherals. Gradual migration to a multi-core architecture and an operating system that supports multiple cores will enable even more significant performance gains (while reducing power consumption).
Just as CPU vendors no longer improve performance by changing megahertz numbers, designers of mobile products should revisit the way they are implemented. Analog-to-digital conversion (ADC) is one such area that begins to make changes in architecture. For example, National Semiconductor has creatively adopted an integrated folding converter that not only greatly increases the speed of operation (gigasamples per second), but also minimizes energy consumption during operation. Traditional flash-type converters are limited by the maximum number of comparators in a single digital-to-analog converter. The number of comparators in a flash DAC is a function of the number of bits output (2n bits). For example, a 10-bit flash digital-to-analog converter would require 1,024 comparators, plus a thermometer code to Gray code to binary conversion circuit and a high precision unified ladder resistor divider.
Folding converters are based on completely different design methods, using a small number of comparators (usually 32 to 64) and "folding" the input signal range so that it is always within the comparator network limits, as shown in Figure 1. Show. The trick here is to compensate for the integral and differential nonlinearities introduced by the folding process. This structure represents a new way of thinking about this thorny problem and greatly reduces the energy consumption required to achieve this. For a dual 10-bit converter (PowerWise ADC10D1000) with gigasamples per second, this approach can reduce power consumption from tens of watts to three watts. This is a power-saving means commonly used in portable imaging, radar and software radio systems.

Digital Power Architecture The architecture is equally important in large ASIC or SoIC designs. The dynamic and static losses associated with CMOS transistors are a common problem even when the geometry of the process is reduced. The energy consumption formula for CMOS is as follows:
E=(aCf _CLK V ² +VI _LEAK )×t _TASK
It contains a frequency-dependent dynamic term and a static leakage current term. Both of these parameters can cause problems as the process size shrinks. Capacitive loads and through currents will decrease, but the number of components on the chip will increase, resulting in higher dynamic power consumption per chip. Short channel effects such as sub-threshold leakage current, leakage source extended leakage current and electron tunneling, and short channel effects such as drain induced barrier lowering (DIBL) are increasingly becoming serious problems in large digital ASIC designs.
When designing large digital systems, timing must be set correctly throughout the run, including supply voltage, process, and temperature fluctuations. This design bottleneck puts power consumption at the worst level, even at the right temperature or in a faster process, and the device will still consume the same amount of energy. One solution is to change the design structure to fit the environment of the device. Adaptive Voltage Scaling (AVS) is one technique for this purpose.
AVS integrates a digital subsystem that monitors the health of the device (which is synchronized with the application digital logic) and dynamically adjusts the supply voltage of different voltage islands within the chip. When the performance requirements change, the AVS logic inside the chip sends an update signal to the external power management device, which is called the energy management unit EMU, and functions to raise or lower the supply voltage of the voltage island. The dynamic term is a function of the square of the supply voltage and therefore provides the greatest gain improvement. Even if the static term is only a linear function of the supply voltage, the reduction in leakage current can still significantly reduce the energy consumption.
The design structure once again shows its importance for the purpose of saving energy as much as possible. In order to maximize the effectiveness of AVS or other voltage regulation techniques, system designers must rethink the division of functional areas to provide separate voltage islands and frequency intervals. If an existing design uses a separate voltage source to power all of the core logic, multiple voltage islands should be used in the new low-power design, where the clock interval will be a limiting factor for dynamic requirements. Moreover, based on slower timing, these voltage islands can utilize voltage regulation techniques or simply employ lower core voltages.
There is a growing demand for portability, especially in the areas of medical, communications and military defense. Engineers need to consider solutions other than power converters to seek greater system efficiency gains. From a system architecture perspective, sometimes innovative approaches are used to achieve certain functions—especially when conventional power converter efficiencies are above 90%, often resulting in significant efficiency improvements. Power technology will eventually catch up with technological advances in process and IC design, but system efficiency remains one of the solutions to extend working hours and reduce heat consumption before engineers have higher energy densities.